1. Field of the Invention
The present invention relates generally to a dry etching apparatus and a method of forming a via hole in an interlayer insulator by using the dry etching apparatus. The present invention is concerned with periodical anisotropic and isotropic etching operations via which an excellent aluminum step coverage of a via hole can be realized.
2. Description of the Related Art
Multilevel interconnections have become essential as semiconductor devices are miniaturized. In order to provide the multilevel interconnections, via holes which are formed in an interlayer insulator play an important role for interconnecting the upper and lower layer conductive lines.
As is well known in the art, a via hole is formed by using both isotropic and anisotropic etching. In order to perform these two etching modes using the same etcher, two types of dry etching apparatus are currently used: one is a triode type etcher and the other is an ECR (Electron Cyclotron Resonance) type etcher.
Before turning to the present invention, it is deemed advantageous to discuss the above-mentioned conventional dry etchers with reference to FIGS. 1 and 2.
FIG. 1 is a schematic cross sectional view of a known triode type dry etcher and associated apparatus. This apparatus is well known in the art and hence only a brief description will be given for the sake of brevity.
The arrangement of FIG. 1 generally includes an etching chamber 10 which is provided with an anode 12, a cathode 14, and a grounded grid electrode 16. The cathode 14 supports a semiconductor wafer 17 which is subject to dry etching. Etching gas is introduced into the etching chamber 10 and is evacuated therefrom via a duct 18. A radio frequency (RF) power source 20 is provided between an impedance matching network 22 and the ground. RF power obtained from the impedance matching network 22 is selectively applied to the anode 12 and cathode 14. The selective application of RF power to the electrodes 12 and 14, is carried out using controlling variable capacitors 24 and 26.
When isotropic etching is to be implemented with the dry etching apparatus shown in FIG. 1, the variable capacitors 24 and 26 are controlled such as to apply RF power only to the anode 12. In this instance, no plasma ions reach the cathode 14 and thus neutral radicals alone play a role in isotropic etching. It is a usual practice to raise the temperature of the cathode 14 during the isotropic etching.
On the other hand, in order to anisotropically etch the wafer 17, the RF power is applied solely to the cathode 14 by controlling the variable capacitors 24 and 26. The etching in this case is reactive ion etching (RIE).
Reference is made to FIG. 2, wherein the second type of known dry etching apparatus which uses electron cyclotron resonance (ECR), is schematically shown.
The ECR type dry etcher, depicted by numeral 30, is provided with an etching chamber (reaction chamber) 34, and a wafer supporting table 36 on which a semiconductor wafer 38 is located. A Waveguide 42 is provided for guiding microwave from a magnetron (not shown) into the etching chamber 34 through a quartz tube or dome 35. The chamber 34 is surrounded by a magnetic ring coil 46. The wafer supporting table 36 is heated by a heater 48 which is connected to a suitable power source (not shown). The temperature of the table 36 is controlled by the heater 48 and cooling water. Further, the wafer supporting table 36 is coupled to a RF power source 50 via an impedance matching network 52.
With this arrangement, a highly ionized plasma is generated at low gas pressures within the chamber 34 under an ECR condition wherein a microwave frequency coincides with the electron cyclotron frequency determined by magnetic flux density. These operations are well known in the art and further descriptions thereof are deemed unnecessary.
In the case where anisotropic etching is to be implemented, the RF power source 50 applies RF power (or bias) to the wafer supporting table 36 via the impedance matching network 52. Contrarily, isotropic etching is performed when the table 36 is grounded. In this case, the table 36 is held at temperatures ranging from 50.degree. C. to 150.degree. C.
Fabrication processes for forming two-level aluminum interconnections, using either of the above-mentioned two dry etchers, will be discussed with reference to FIGS. 3A-3C. In order to establish the two-level interconnection, a plurality of via holes are formed in a single interlayer insulator.
As shown in FIG. 3A, a field insulating layer 60 is selectively deposited on a semiconductor substrate 62, after which a first interlayer insulator 64 is formed on the entire surface thereof. An aluminum layer (not shown) is formed by sputtering so as to cover insulator 64 and the exposed portion of the substrate 62. Thereafter, the aluminum layer thus formed undergoes patterning, using photolithography, to form the first level aluminum interconnecting lines 66a, 66b and 66c. The entire surface of the wafer is then covered with a second insulating layer 68 whose upper surface is essentially flat. The thickness of the insulating layer 68 above each of the aluminum lines 66a and 66b is depicted by Ha, while the thickness of the insulating layer 68 above the aluminum line 66c is depicted by Hb. Following this, a photoresist film 70 is patterned on top of the insulating layer 68 in preparation for the formation of via holes in the subsequent steps shown in FIGS. 3B and 3C.
The wafer which has been subject to the processes discussed with FIG. 3A, is then placed in one of the two dry etching apparatuses shown in FIGS. 1 and 2.
The device is isotropically etched using Ar+CF.sub.4 gas. That is, the isotropical etching is implemented by F or CFx radicals. The amount of isotropical etch of the insulating layer 68 in the vertical and lateral directions Y1 and X1, are approximately identical.
Subsequently, the wafer is anisotropically etched using F or CFx ions within the same dry etching apparatus as the wafer has been isotropically etched. When the insulating layer 68 undergoes anisotropical etching in the vertical direction by the amount of (Ha-Y1), two via holes VH1 and VH2 are formed which respectively reach the surfaces of the aluminum lines 66a and 66b. During the anisotropic etching, aluminum sputtering occurs at the surfaces of the aluminum lines 66a and 66b due to ion bombardment. The sputtered aluminum reacts with F or CFx ions. Thus, aluminum fluoride is generated which accumulates on the walls of the via holes VH1 and VH2. The accumulated aluminum fluoride is denoted by numeral 72. It should be noted that the aluminum fluoride does not accumulate on the surfaces of the aluminum lines 66a and 66b.
After completion of the above-mentioned processes, the wafer is subject to anisotropic etching to form a via hole VH3 by etching the insulating layer 68 by the amount of (Hb-Ha) in the vertical direction.
After developing the above-mentioned via holes VH1-Vh3, the photoresist film 70 and the aluminum fluoride 72 are removed. Then, an aluminum layer is deposited over the entire top surface of the device, after which the aluminum layer is patterned, using lithography, to provide three interconnecting portions 72a, 72b and 72c which are respectively coupled to the aluminum lines 66a, 66b and 66c, as shown in FIG. 3C.
With the above-mentioned conventional dry etching, only one switching of the two dry etching modes is possible. In more specific terms, the time duration of each of the two etching steps is very short (for example, 300 ms). Accordingly, it is practically impossible to switch over between isotropic and anisotropic etching two or more times.
If the via holes are formed using one isotropic etching step and one anisotropic etching step (viz., only one switching from one etching mode to the other), the shoulder of the via hole VH3 at the second insulating layer 68 is insufficiently covered with aluminum. This insufficient step coverage is induced in the case where the depth of the vertical portion of the via hole (such as VH3) is large relative to the diameter thereof. This poor step coverage tends to cause a breakdown of the multilevel interconnection.
In order to overcome the aforesaid step coverage problem, one method has been proposed wherein the internal insulator 68 is further anisotropically etched such that the etching depth (depicted by Y2) is larger than Y1 and less than Ha (viz., Y1&lt;Y2&lt;Ha), as schematically shown in FIG. 4. However, this approach induces another problem because the distance between the via holes is undesirably narrowed to an extent that the aluminum interconnections 72a and 72b (FIG. 3C) are liable to contact each other. This problem may be eliminated by providing sufficient separation between the aluminum lines 66a and 66b. However, this technique inversely affects the current tendency of device miniaturization.
Further, in order to ensure that the bottom of the via hole VH1 (or VH2) is located on each of the aluminum lines 66a and 66b, it is necessary to widen the lines 66a and 66b as shown in FIG. 5. This also undesirably induces an obstacle to device miniaturization.